A semiconductor memory has redundancy memory cells for relieving a defect and improving yields. The redundancy memory cells are accessed instead of real memory cells based on a defect address programmed in a fuse or the like. Before a defect is relieved, the redundancy memory cells may not be accessed and may not undergo an operation test, either. For example, in order to cause the execution of the operation test of the redundancy memory cells before the defect is relieved, a test signal is supplied to an external terminal. Related arts are discussed in Japanese Laid-open Patent Publication No. 2006-73111, No. 07-226100, and No. 06-243698.
To shorten the test time of the semiconductor memory, a compression test in which one write data signal is written to a plurality of memory cells having different addresses is executed. A related art is discussed in Japanese Laid-open Patent Publication No.
When the test signal is supplied to the external terminal, the semiconductor memory enters a dedicated test mode and the operation test of the redundancy memory cells is executed one by one. There has been proposed no method for executing the operation test of the redundancy memory cells in a compression test. Therefore, there has been a problem that the operation test of the redundancy memory cells takes a lot of time.